1. Field of the Invention
The present invention generally relates to supporting virtual vector operations on a multi-threaded microprocessor. More specifically, the present invention relates to a technique for efficiently executing vector operations by mapping them across a set of threads that execute in parallel on the multi-threaded microprocessor.
2. Related Art
Vector processors are designed to improve computation for highly-parallel applications such as scientific computing. A vector instruction specifies an operation that will be repeated for an entire vector of independent data values, thereby essentially describing a large number of operations in a single instruction. Since a vector instruction executes the same operation on many independent pieces of data with known memory access patterns and no data hazards, a vector processor can leverage very deep pipelining to make such operations execute faster than on a non-vector processor.
The complexity and high cost of vector processors as well as advances in designs for pipelined multi-threaded processors have caused vector processors to be used less frequently. However, while the performance of multi-threaded microprocessors has improved dramatically, their lack of support for vector instructions makes exploiting parallel operations difficult in many situations. This is especially true for multi-threaded, multi-core processors, which include multiple, separate processors onto a single chip. These factors require programmers to create complex code for multiple threads in order to keep the processor busy, and have resulted in an increase in program complexity and programming difficulty.
Hence, what is needed is a method and an apparatus for supporting vector operations on a multi-threaded microprocessor.